About the Course
This course focuses on the basic architecture, simulation and hardware of digital system design implementation using Spartan 6 FPGA Board and Artix 7 FPGA using Xilinx ISE tool and VIVADO respectively. This course requires prior knowledge of Digital electronics. The learning outcome of this course is that, students are able to design, simulate and implement any problem related to digital design both from research and industrial perspective with proper real time specifications. The main focus of this course is to make students design, simulate and implement from fundamental logic gates to sequential circuits with some of mini projects using SPARTAN 6 FPGA Board and Artix 7 FPGA. The student will be able to implement the design on higher version of tools and boards with little modifications.
1) Day 2, Day 3 and Day 4 quiz/MCQ – 50%
2) Evaluation of Project 1 – 25%
3) Evaluation of Project 2 – 25%
Course Objectives(What will you learn)
Upon completion of this course, students will be able to design, a digital system, Simulate using Verilog and implement the same using latest FPGA tool. They are able to take up real time project with respect to any digital system implementation using FPGA
Who should attend
4thand 6th sem ECE, CSE & EEE Students.
Out station students / candidates have to make their arrangements for accommodation and boarding
Course Outline and schedule
Session 1: Objectives of the course, Overview of the course content, FPGA basics, Xilinx ISE Tool and Verilog introduction and coding for basic gates.
Session 2: Simulation and Hardware implementation of combinational circuits examples using Spartan 6 with Xilinx ISE Tool.
Session 3: Simulation and Hardware implementation of Sequential circuit examples using Spartan 6 with Xilinx ISE Tool.
Session 4: FSM concepts, Simulation and Hardware implementation of Digital circuit by FSM examples using Spartan 6 with Xilinx ISE Tool.
Session 1:Evaluation by Quiz/MCQ about the previous day session. Designing a parameterized (N-bit) circuits using Verilog and Implementation on ARTIX-7, Designing a Verilog model of the complex multiplier Data-path and control path using FSM.
Session 2: Writing Stimulus Block Using TASK and FUNCTION in verilog.
Session 3: Interfacing ARTIX-7: Implementation of ALU in Xilinx Artix-7 FPGA board and displaying the results using LED interface
Session 4: Design of various counter and implementation on Artix-7 FPGA., Sequential Shift Registers.
Session 1:Evaluation by Quiz/MCQ about the previous day session. LED Interface of counters and implementation using FPGA.
Session 2: The real time project based on communication protocol is discussed for design, simulation and implementation using FPGA.
Session 3: Hands on session on the communication protocol based project continues.
Session 4: The real time project based on IP core is discussed for design and implementation. Hands on session on the project.
Session 1:Evaluation by Quiz/MCQ about the previous day session. Design of a VGA Controller using FPGA. The specifications are given and students should design the controller using above specifications.
Session 2: Simulation and Implementation of the VGA controller with MATLAB interface is discussed (It gives the idea of image capturing by FPGA using VGA).
Session 3: Specifications and requirements for a vending machine mini project. The participants are required to design and simulate the above task.
Session 4: Hands on sessions on vending machine project continues and participants are allowed to implement the same using FPGA.
Session 1:The specifications and problem requirements for a project 1 is given. The participants are required to design and implement the same.
Session 2: Hands on session on the project 1 continues and finally assessment of the project 1.
Session 3: The specifications and problem requirements for a project 2 is given. The participants are required to design and implement the same.
Session 4: Hands on session on the project 2 continues and finally assessment of the project 2.